GaN-based permeable base transistor and method of fabrication

ABSTRACT

An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/527,238, filed Dec. 4, 2003, which is herein incorporated in itsentirety by reference.

FIELD OF THE INVENTION

The invention relates to transistors, and more particularly, topermeable base transistors.

BACKGROUND OF THE INVENTION

There is increasing need for new devices that can operate at frequenciesgreater than 1 GHz. The wide bandgap semiconductor gallium nitride (GaN)has received much interest in the last decade as a material for highefficiency, high power microwave devices due to its high breakdown fieldand electron saturation velocity, and low thermal generation rate.Unfortunately, there is no native substrate on which to grow GaN deviceepilayers, hence the films are grown heteroepitaxially on sapphire orsilicon carbide substrates.

Such growth results in films with considerable vertical threadingdislocation densities that limit electron mobility in lateral devicessuch as metal semiconductor field effect transistors (MESFETs) or highelectron mobility transistors (HEMTs). Yet the vertical mobility isenhanced. This physical attribute together with the material propertiespreviously mentioned makes GaN a highly suitable material for apermeable base transistor (PBT).

The PBT is device very similar to the MESFET but with vertical transportinstead of lateral, and has received much attention in the last quarterof a century due to its potential as a high power, high frequency, andhigh temperature-operating device. PBTs were suggested as early as 1964,and are typically fabricated using silicon, cobalt disilicide, galliumarsenide, silicon carbide, nickel phthalocyanine, and copperphthalocyanine.

Due to the early stage of development in the GaN growth andunderstanding of the material properties, PBTs fabricated with GaN haveonly recently been attempted. Reported modeling simulations of a GaNbased PBT with a cut-off frequency (f_(T)) as high as 24.8 GHz andmaximum frequency of oscillation (f_(max)) of 75.2 GHz. Such performanceis relatively limited.

What is needed, therefore, techniques for making high power GaN PBTsusing GaN.

SUMMARY OF THE INVENTION

One embodiment of the present invention provides an etched groovedGaN-based permeable-base transistor device. The device includes a GaNemitter region (e.g., having a thickness of about 6 to 10 μm) that isgrown (e.g., on (0001) sapphire) using hydride vapor-phase epitaxy(HVPE). This emitter region may further include He implantation underbase and collector contact pads to provide pad isolation (e.g., implantangle of about 7°). The device further includes a GaN base region (e.g.,having a thickness of about 1 to 2 μm) that is grown on the GaN emitterregion using molecular beam epitaxy (MBE). The device further includes aGaN collector region (e.g., having a thickness of about 0.1 to 0.3 μm)that has a plurality of collector fingers The collector region is grownon the GaN base region using MBE. In one such particular embodiment, thecollector fingers have finger sidewall angles of about 80° to 85° for1:1 and 1:3 finger spacing. In another particular such embodiment, thecollector region has a collector pad region and a plurality of collectorfingers, wherein the collector fingers have a first height in thecollector pad region and a second height out of the collector padregion, with the first and second heights configured so as to preventdisconnect between the collector fingers and the collector pad region.For instance, the difference in the first and second heights could bethe thickness of one layer of collector pad metal.

Another embodiment of the present invention provides a method forfabricating an etched grooved GaN-based permeable-base transistordevice. One such embodiment of the method includes seven mask levels,including: Level 1—He implant mask; Level 2—nitride isolation pad; Level3—collector ohmic pad mask; Level 4—e-beam lithography of collectorfingers for liftoff; Level 5—base recess and metallization; Level6—emitter and device isolation etch, emitter ohmic; and Level7—microwave test pad metal deposition. Note that not all seven masksneed to be used in practicing other embodiments of the presentinvention.

The features and advantages described herein are not all-inclusive and,in particular, many additional features and advantages will be apparentto one of ordinary skill in the art in view of the drawings,specification, and claims. Moreover, it should be noted that thelanguage used in the specification has been principally selected forreadability and instructional purposes, and not to limit the scope ofthe inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a side and top perspective view of a GaN PBT deviceconfigured in accordance with an embodiment of the present invention.

FIG. 1 b is a vertical cross sectional view of the GaN PBT device shownin FIG. 1 a.

FIG. 2 a demonstrates the material structure of a GaN PBT deviceconfigured in accordance with an embodiment of the present invention.

FIG. 2 b illustrates various views of a GaN PBT device used toillustrate fabrication processes configured in accordance with anembodiment of the present invention.

FIGS. 3 a through 7 illustrate a seven mask process flow for fabricatingan GaN PBT and variations thereof in accordance with an embodiment ofthe present invention.

FIG. 8 is a top plan view SEM picture of a completed GaN PBT devicefabricated in accordance with an embodiment of the present invention.

FIG. 9 (a and b) are SEM pictures showing a GaN PBT device fabricated inaccordance with an embodiment of the present invention, with FIG. 9 ashowing a 1:1 finger pitch, and FIG. 9 b a 1:3 finger pitch.

FIG. 10 is a graph showing a I-V characteristic curve of a GaN PBTdevice fabricated in accordance with an embodiment of the presentinvention.

Note that the various features shown in the Figures are not drawn to anyparticular scale. Rather, the Figures are drawn to emphasize featuresand structure for purposes of explanation. The actual geometries andscale of the pertinent features and structure will be apparent in lightof this disclosure.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention provide a design and method offabrication of an etched grooved GaN-based permeable-base transistorstructure. Process flow details regarding passivation, active region dryetching, and a mask set designed for PBT fabrication are disclosed. Themask set is configured to provide discrete PBT devices with a range ofgeometries for different frequency and power level operation, and highquality metal contacts to the various GaN layers.

One particular embodiment is fabricated using n-type GaN grown byhydride vapor phase epitaxy (HVPE) and molecular beam epitaxy on thickHVPE GaN quasi-substrates. The fabrication process employs isolationpads via helium (He) implantation and silicon nitride (SiN) deposition,as well as sub-micron chlorine-based high density inductively coupledplasma (ICP) etching of collector fingers patterned via e-beamlithography. Base Schottky contacts are deposited on the etched GaNlayer prior to ohmic metal deposition so Schottky contacts on dry etchedsurfaces as well as low temperature annealed (0-500° C.) Schottky andohmic contacts are characterized for their performance.

The resulting high power GaN PBT device has a cutoff frequency f_(T) ofabout 134 GHz and a maximum frequency f_(max) of about 500 GHz. Thedevice has a breakdown voltage of about 50V and a g_(m) of 70 mS/mm.Analysis of the device topology shows smooth etched finger structuresand base layer surface with finger sidewall angles of about 80° to 85°for 1:1 and 1:3 finger spacing. Specific contact resistivities of about3×10⁻⁶Ω·cm² for the ohmic contacts were achieved with Ti/Al/Ni/Aumetallization scheme. DC testing of these example devices show a currentdensity J_(S) as high as 518 mA/mm², and a collector current I_(C) ofabout 140 mA/mm, both at V_(CE) of 5V and V_(BE) of +0.5V. Thetransconductance g_(m) achieved is about 111 mS/mm in the measuredcollector-emitter bias range. These actual results are comparable,within the measurement tolerance, to physics-based modeling results.

Other configurations will be apparent in light of this disclosure. Inany such cases, a GaN PBT is provided that combines the high breakdownfield of GaN and the good frequency response of a PBT. Applications foruse include, for example, millimeter-wave power applications.

PBT Structure

Generally, there are two types of PBTs: etched groove and embedded orovergrown. In the case of etched groove, many submicrometer bases lay inetched grooves between ridge-like emitter contacts. In the case ofembedded or overgrown, the base is completely buried inside thesemiconductor lattice by epitaxial regrowth of the semiconductor.Embodiments of the present invention are directed to the etched groovetype PBT.

The operation of the PBT is very similar to that of the MESFET exceptthat the PBT is a vertical device and the MESFET is a lateral carrierdevice. In the PBT, the current flows perpendicular to the materialsurface. With this type of device, the thickness of the grown materiallayers can be altered to vary the device characteristics. In addition,the PBT is unipolar with a relatively short base length compared to thebase length of a MESFET.

FIGS. 1 a and 1 b illustrate an etched groove PBT with metal contactconfigured in accordance with one embodiment of the present invention.To fabricate an etched groove PBT with suitable electricalcharacteristics, two conditions should be met: the spacing between metalfingers should be such that the two depleted zones meet (e.g., spacingbetween metal fingers smaller than 1 μm); and the leakage current ofboth base-collector and base-emitter Schottky diodes should beminimized. This requires a relatively large Schottky barrier height(Φ_(B)>1 eV) on the material with which it is in contact. Thissubmicrometer-periodicity Schottky-barrier grating is used to modulatethe vertical flow of electrons.

As shown in FIGS. 1 a and 1 b, the top ohmic layer serves as thecollector contact (on top of the device fingers). The bottom and middleohmic layers serve as the emitter and base contacts, respectively, whichare deposited in two separate etched regions. Since the gate length(l_(g)) is defined by the thickness of the Schottky metal in the baseregion, l_(g) can be realistically fabricated as smaller than 0.1 μm(the limit of most conventional transistors). Because of this, theeffective channel length is mainly controlled by the depletion widthtowards collector and emitter.

The device was fabricated starting from a GaN quasi-substrates (e.g., 6to 10 μm) grown on (0001) sapphire using a hydride vapor-phase epitaxy(HVPE) reactor. Note that this GaN quasi-substrate layer also serves asthe emitter region for the PBT. In one embodiment, this layer isauto-doped n-type with a silicon (Si) carrier concentration of about5×10¹⁸ cm⁻³. Atomic force microscopy (AFM) studies on the GaNquasi-substrates show a step-flow growth mode with atomically smoothterraces or “fingers” of 0.2 μm width and step-height of 2 monolayers.RMS roughness of 0.45 nm was obtained over a 10×10 μm area.

The base and collector epilayers of this embodiment are 1.3 μm and 0.2μm thick, respectively. The layers can be grown by plasma-enhancedmolecular beam epitaxy (MBE) carried out, for example, in a Varian Geniisystem. Other such systems can be used here as well. Seamless epitaxy ofGaN via MBE on GaN quasi-substrates can be achieved by growing theepilayers in group III-rich conditions. These base and emitter layersreplicate the underlying GaN quasi-substrate layer without renucleation.The base and collector layers are doped with silicon (Si) to carrierconcentrations of 5×10¹⁶ and 5×10¹⁸, respectively.

When the PBT is in ON condition, the majority carriers flow from emitter(held at ground potential) to collector (biased at positive potential).Under normal operation, the Schottky barrier is reverse-biased by anegative base-to-emitter voltage. A voltage dependent depletion regionforms beneath the Schottky barrier. This constricts the effective areaof the n-channel (reducing the depletion region on either side of theemitter finger), causing the channel to open and the collector currentto vary with applied base bias.

In a PBT, the base bias induces a potential barrier under the collector.Near pinch-off, electrons that are injected from the emitter areaccelerated by the collector bias, and pass across the potentialbarrier. At higher collector biases, the thermionic emission currentrises exponentially with applied collector bias eventually becomingspace charge limited, resulting in a triode mode device operation, wherethe collector current does not saturate at high collector voltages.

When a negative bias is applied to the collector, the depletion regionexpands and current flow through the channel is restricted. This willultimately result in pinch off of the channel, and turn off of the PBT.Pinch off can be approximated using the equation:

$V = \frac{1{qNa}^{2}}{2ɛ_{r}ɛ_{0}}$where q is the charge of an electron, a is the channel thickness (or, inthe case of a PBT, half the width of 1 finger), ε(r) is the relativepermittivity of the material, and ε(0) is the permittivity of vacuum.

Fabrication Methodology

FIGS. 3 a through 7 demonstrate a process flow for the fabrication of aGaN PBT in accordance with one embodiment of the present invention. Thisprocess flow includes all steps required to fabricate the device, aswell as the design of a photolithography mask set drawn using AutoCAD.Various process alternatives are also provided.

The GaN PBT, because it is based on vertical transport, has threedistinctly doped layers versus the two of lateral transistor devices forthe metal contacts and the device itself to perform optimally. Thematerial structure to be employed in the GaN PBT, in accordance with oneembodiment of the present invention, is shown in FIG. 2 a.

Due to the lattice mismatch of GaN grown on sapphire or SiC, the bottomn⁺ layer is deposited thick (e.g., n⁺5×10¹⁸ cm⁻³, HVPE) to keep thevertical threading dislocations minimal. The layer structure is chosenbecause the heavily doped regions will be used for ohmic contacts andthe lightly doped region will be used for a Schottky contact toadequately pinch off for a given range of high frequency operation. Thedesired blocking voltage of the transistor determines the thickn-region. The final structure will look similar to that shown in FIG.1b, where the material layers are the same as in FIG. 2 a.

Note that a full PBT will have a plurality of the collector fingers, andis this particular case. Only three are shown in FIG. 1b for the purposeof illustration. In one particular embodiment, the full PBT device has20 collector fingers, each surrounded by two base regions to control thewidth of the channel, as shown in FIG. 1 b. It will be appreciated that,in developing a process for a PBT device, it is necessary to havetolerances to variability in the semiconductor material characteristicsand fabrication process. Some tolerances that are used herein arepassivation layers, implantation, and pre-metal deposition treatments.

When referring to example embodiments of the PBT process describedherein, the following views shall be discussed and are illustrated inFIG. 2 b: view 1 is the overall top view; view 2 is the cross sectionthrough the collector RF probe pad; view 3 is the cross section throughthe collector ohmic pad; view 4 is the cross section through the basecollector fingers; and view 5 is the cross section through the base RFprobe pad.

This is a seven-mask process flow that is the baseline for all of thesubsequent versions. Various modifications and details not included inthis version will be apparent in light of this disclosure.

This particular embodiment begins with the HVPE growth of 10 μm ofheavily doped (e.g., 2×10¹⁸ cm⁻³ to 5×10¹⁸ cm⁻³) n-GaN followed by 2 μmof MBE grown, lightly doped (e.g., 2×10¹⁶ cm⁻³ to 5×10¹⁶ cm⁻³) n-GaN and0.3 μm of MBE grown, highly doped (e.g., 2×10¹⁸ cm⁻³ to 5×10¹⁸ cm⁻³)n-GaN. The silicon nitride deposition (to be discussed in turn) is topassivate the sidewalls of the collector fingers to prevent shorting ofthe base to the collector if metal accidentally deposits on thesidewalls.

The mask levels for this example process are shown here in Table 1:

TABLE 1 Level 1 He implant mask Level 2 Nitride isolation pad Level 3Collector ohmic pad mask Level 4 E-beam lithography of collector fingersfor liftoff Level 5 Base recess and metallization Level 6 Emitter anddevice isolation etch, emitter ohmic Level 7 Microwave test pad metaldeposition

The process flow will now be discussed in steps, and with reference tothe FIGS. 3 a through 7. Note that the following steps are notnecessarily intended to implicate any rigid order of performance, andother embodiments may have the steps performed in a different order,with a similar end product produced.

Step 1: Perform RCA wafer clean. The purpose of the RCA wafer clean isto remove organic contaminants (e.g., dust particles, grease or silicagel) from the wafer surface, as well as any oxide layer that may havebuilt up, and any ionic or heavy metal contaminants.

Step 2: Open windows for helium (He) implantation using opticallithography. Due to the fact that the PBT is a “normally-on” device, thesemiconductor material is conducting by default. Thus, an insulatinglayer is used to isolate the pads from the device. In this particularembodiment, the insulating layer is provided with He implantation. FIG.3 a shows the optical lithography for He implantation of this step. Ascan be seen, the photo resist (PR) is shown is each of the views inlocations where no He implantation is desired. In one particularembodiment, the wafer is patterned with about 9 μm photo resist for theHe implantation.

Step 3: Perform He²⁺ implantation at about 250 keV, 1.35 μm isolationdepth (determined from a TRIM calculation). FIG. 3 b shows the locationsof He implantation with the diagonal striping. In one particularembodiment, a dose of about 1×10¹⁵ cm⁻³ was targeted with anacceleration voltage of 180 keV at an implant angle of 7°. With theseparameters, TRIM simulations estimated an implant depth of about 2 μm.

Step 4: Strip the photo resist mask. The resulting structure afterstripping is shown in FIG. 3 c.

Step 5: Open windows for thin, high quality silicon nitride pad(SiN_(x)), about 1000-2000 Å thick, using optical lithography. FIG. 3 dshows the optical lithography for the SiN_(x) pad of this step.

Step 5a: Perform deposition of high quality SiN_(x) pad, 1000-2000 Åthick. This SiN_(x) layer serves as the second electrical isolation forthe collector and base contact pads. FIG. 3 e shows the resultingstructure after the SiN_(x) deposition of this step. In one particularembodiment, 1000 Å of high quality SiN_(x) pads were deposited on top ofthe He-implant region via plasma enhanced chemical vapor deposition(PECVD).

Step 5b: Perform lift-off of high quality silicon nitride pad, 1000-2000Å thick. FIG. 3 f shows the resulting structure after the SiN_(x)lift-off of this step, where all SiN_(x) deposited on top of photoresist is removed.

Step 6: Open windows for Ti metal pad using optical lithography. FIG. 3g shows the optical lithography for the Ti pad of this step.

Step 6a: Perform Ti metallization. FIG. 3 h shows the resultingstructure after the Ti metallization of this step. In one particularembodiment, Ti/Au (500 Å/1000 Å) collector metal pads are depositedusing e-beam evaporation.

Step 6b: Perform lift-off of Ti metallization. FIG. 3 i shows theresulting structure after the Ti metallization lift-off of this step,where all Ti deposited on top of photo resist is removed.

Step 7: Perform E-beam lithography of collector fingers and forself-aligned base recess and metallization. FIG. 3 j shows the E-beamlithography of the collector fingers of this step. In one particularembodiment, the wafer is patterned with e-beam lithography using PMMAphoto resist (about 0.14 μm) for the metallization of the collectorfingers.

Step 7a: Perform ohmic metallization of collector. Prior tometallization, a 1 minute HCl:DI H₂0 (1:1) dip is used for removingcontaminants on the semiconductor surface. Although not mentioned inother steps, this can beneficially be used for all metal depositions onsemiconductor material. FIG. 3k shows the resulting structure after theTi/Ni metallization of this step. In one particular embodiment, themetal scheme used for the collector fingers is Ti/Ni with thicknesses of100 Å and 400 Å, respectively. With this arrangement, Ti acts as themetal contact, while Ni serves as the base shallow etch mask.

Step 7b: Perform lift-off of ohmic metallization of collector. FIG. 3 mshows the resulting structure after the Ti/Ni metallization lift-off ofthis step, where all Ti/Ni deposited on top of photo resist is removed.In one particular embodiment, each collector finger is about 0.2 μm wideand 230 μm in length. Since only 200 μm of this length covers eachfinger active region of the device, the total finger area is 40 μm².Each device has 20 fingers either with a 1:1 pitch (evenly spaced) or1:3 pitch.

Step 8: Open windows for a Ti cap in collector pad region using opticallithography. FIG. 3 n shows the optical lithography for the Ti cap ofthis step.

Step 8a: Deposit thin Ti cap in collector pad region again to preventcollector metal fingers from peeling upward and losing contact to thepad. FIG. 3 p shows the resulting structure after the Ti metallizationof this step. In one particular embodiment, Ti/Au (500 Å/1000 Å)collector metal caps are deposited using e-beam evaporation.

Step 8b: Perform lift-off of the thin Ti cap in collector region. FIG. 3q shows the resulting structure after the Ti metallization lift-off ofthis step, where all Ti deposited on top of photo resist is removed.

Step 9: Open windows for the base recess/metallization (collector linesare part of mask) using optical lithography. FIG. 3 r shows the opticallithography for the base recess/metallization of this step.

Step 9a: Perform a high density plasma etch to recess the base layer ton⁻ layer (e.g., about 0.5 μm). FIG. 3s shows the resulting structureafter the high density plasma etch in the base region of this step. Inone particular embodiment, the wafer is etched using a custom-builtinductively coupled plasma (ICP) etching system utilizing pure Cl₂chemistry. Etching can be performed at a chamber pressure of about3.8×10⁻³ torr, 350 W ICP power and about −400 V chuck bias with a rampdown to about −200V bias for the last minute of the etch. The ramp downetches a layer of material damaged by plasma leaving behind undamagedGaN for subsequent metal contact deposition. This etch-damage removalenables excellent ohmic electrical characteristics. Approximately 0.5 μmetch depth is achievable.

Step 9b: Perform conformal SiN_(x) deposition for spacer and sidewallpassivation. This layer prevents shorting between the base and collectorif metal accidentally deposits on the finger sidewalls. FIG. 3 t showsthe resulting structure after the SiN_(x) deposition for spacer andsidewall passivation of this step. In one particular embodiment, theconformal SiN layer is less than 500 Å.

Step 9c: Perform directional etch to remove SiN_(x) on parallelsurfaces. FIG. 3 u shows the resulting structure after the directionaletch for SiN_(x) removal of this step. In one particular embodiment, adirectional reactive-ion etching (RIE) of the SiN planes parallel to thesurface was used to expose the base layer between the fingers.

Step 9d: Perform base metallization (Pt/Ni). FIG. 3 v shows theresulting structure after the base metallization of this step. In oneparticular embodiment, the base contact was deposited using Ni/Pt/Au(Schottky contacts) having layers of thickness 100 Å/400 Å/100 Å,respectively.

Step 9e: Perform lift-off of base metallization (Pt/Ni). FIG. 3 w showsthe resulting structure after the base metallization lift-off of thisstep.

Note that a post Schottky deposition anneal is used to alloy the ohmiccontacts. This is because the Schottky metal is deposited before theemitter ohmic metal. A low temperature anneal does not substantiallyalter the forward bias behavior of the Schottky contacts, but decreasesthe reverse leakage current. Further note that the Schottky contacts arethe contacts in the base region). In one particular embodiment, ananneal for about 60 seconds at 500° C. is used to maintain low reversecurrent leakage while providing low contact resistance.

Step 10: Open emitter etch/contact window using optical lithography.FIG. 3 x shows the resulting structure after the optical lithography foremitter etch of this step. In one particular embodiment, the wafer ispatterned with a thick photoresist (e.g., about 4 μm) for a deep etch of2 μm to 3 μm down to the emitter layer via ICP etching.

Step 10a: Etch emitter recess to bottom, HVPE n⁺ GaN quasi-substratelayer (e.g., about 2.5 μm). FIG. 3 y shows the resulting structure afterthe etching of the emitter recess of this step.

Step 10b: Perform emitter ohmic metallization. FIG. 3 z shows theresulting structure after the emitter ohmic metallization of this step.In one particular embodiment, the emitter ohmic contacts were depositedusing a Ti/Al/Ni/Au metal scheme having thicknesses of 300 Å/1500 Å/400Å/1500 Å, respectively.

Step 10c: Perform lift-off of emitter ohmic metallization. FIG. 3 aashows the resulting structure after the emitter ohmic metallization ofthis step.

Step 11: Open windows for RF test pad metallization using opticallithography. FIG. 3 bb shows the resulting structure after the opticallithography of this step.

Step 11a: Deposit RF test pad metal. FIG. 3 cc shows the resultingstructure after the deposition of test pad metal of this step. In oneparticular embodiment, this metal includes an adhesion layer (e.g.,titanium or nickel) and a thick gold (Au) capping layer, since Au is agood microwave conductor and prevents oxidation.

Step 11b: Perform lift-off RF test pad metal. FIG. 3 dd shows theresulting and final structure after the RF test pads liftoff of thisstep.

Variations on Fabrication Methodology

A first variation on the PBT fabrication methodology deals with thedeposition of the SiN_(x) in step 5. In more detail, a conformaldeposition of SiN_(x) over the entire wafer followed by photo resistpatterning and wet chemistry etch to remove the SiN_(x) from theunwanted areas may be more desirable, since SiN_(x) is sometimesdifficult to remove via liftoff. In this case, the SiN_(x) is about 1000Å thick, and the wet chemical etch will provide a shallow slope on thesidewalls which will ensure metal continuity from the collector fingersto the contact pad. In addition, the metal pad on top of the collectorregion can be altered to Ni/Pt because of the new Schottky metal on thecollector fingers.

The electron beam lithography can also be changed, to provide a secondvariation. In particular, instead of opening up windows for the fingersand depositing metal as previously described in steps 7 through 7b, alarge window can be opened. For example, FIG. 4 shows the e-beamlithography for opening a large base window in accordance with one suchembodiment of the present invention. This window would be used for baserecess and metallization as well as collector finger metallization. Thiswill ensure that the metal on the collector fingers is not very thick,thus minimizing the chance of connection between the various fingers.

Following base recess, all steps would be similar to those previouslydiscussed until step 9d, where the Schottky metal deposited would be themetal for both the base region and collector fingers. The Schottky metalwould be feasible as the collector metal because of ballistic electronsthat could pass the potential barrier. In addition, the Ti capping layeron the collector contact in steps 8 through 8b can be omitted, in thisparticular variation.

In a third variation of the fabrication process, a “0” level Ti/Pt layercan be used. In more detail, note that the first layer (step 3) is a Heimplantation, which requires alignment for further steps in the process.In particular, implanted He areas are not distinguishable under opticalalignment. For this reason, a “0” level mask for subsequent optical andelectron beam alignment was added. The metal to be used for enablingoptical alignment is titanium (Ti) followed by platinum (Pt). In onesuch embodiment, this “0” level mask is a Ti/Pt layer of about200-500/1500 Å, respectively. These metals are chosen because of Ti'sgood adhesion to GaN and Pt is a good alignment metal for e-beam writers(because it is high Z). Crosses for optical alignment and squares fore-beam alignment are thus provided.

The thick Pt was found to work best for this e-beam writing system.Also, it was found that the He²⁺ implantation given in step 3 wouldpenetrate the photo resist about 3.50 μm based on a TRIM calculation ofRp+ΔRp (the ion range and range straggling). This shows that a thickresist, such as AZ4620, is needed. In addition, the SiN_(x) etch can bedone via a wet chemistry of NH₄F, which will leave a shallow slope onthe nitride walls due to the slow etching and isotropy characteristic ofwet chemistry etches. The e-beam photo resist, PMMA, is not intended tobe a dry etch mask and for this reason, cannot be used as previouslygiven in step 7. For this reason, only the collector fingers shall beopened.

In one such particular embodiment for high power operation, 20 fingerscould be used. These fingers shall be 40-200 μm long and varying width(0.15-0.3 μm). The metal on top of these fingers can be, for example,Schottky, Ni/Pt/Ni (200/500/500 Å), where the final Ni layer is used asan etch mask since it was found to withstand a chlorine etch well. Thisis followed by the base etch similar to step 9. The settings of thisetch shall be ICP, ˜0.43 μm in depth using pure Cl₂ chemistry, 400 W ICPpower, and 200 eV ion energies. The low bias voltage is used to providea slow and accurate etch depth. The structure resulting from the baseetch following collector metal deposition (with photo resist) is shownin FIG. 5 a. The decreased etch depth (0.43 μm) is due to an additionaletch step that is needed and will be described next.

A base metal deposition as given in step 9b isolates the base metal fromthe GaN material on the sides of the collector fingers so an additionaletching after the SiN_(x) deposition is needed to expose the sidewallsof the collector fingers, and to allow better base metal contact and,therefore, better base voltage control of the collector currentresulting in higher transconductance in the device. This depositedSiN_(x) is, for instance, less than 500 Å via PECVD. This thickness isdecreased since the minimum base region width is 1500 Å and 1000 Å ofSiN_(x) on both sides would completely close the base region. Thisadditional etch is a two-stage etch.

First, a CH₄—O₂ mix is used via RIE to directionally remove the SiN_(x)since Cl₂ has a much faster etch rate on GaN than on SiN_(x). FollowingSiN_(x) removal, an ICP base etch for collector finger contact will beused to etch the GaN 0.07 μm as shown in FIG. 5 b. The 0.07 μm depth isexactly the thickness of the subsequent metal deposition to preventshorting of any metal that accidentally deposits on the sidewalls or incase the metal deposition is slightly thicker than expected. After thisadditional base etch for collector finger contact, the base ismetallized with Ni/Pt (300/400 Å). Following this, all steps can be aspreviously discussed.

A fourth variation of the fabrication process includes the initialdeposition of Ti/Al/Pt alignment markers. The addition of Al is tocreate an ohmic contact at the first layer for ohmic circulartransmission line measurement (CTLM) and Schottky diode test structuresthat will be employed since the e-beam writer cannot write large areasduring definition of the collector regions (otherwise, the first ohmicdeposition). The addition of Al will not affect the e-beam alignmentwith the thick Pt (e.g., 1500 Å) deposited. He implantation under bothbase and collector contact pads is used due to the high conductivity ofthe material. This is shown in FIG. 6 a. The placement of the e-beamalignment markers is also given. Each alignment box is 4 μm×4 μm. Notethat they are 75 μm from the region to be written, due to the stringentrequirements of the ebeam writing tool.

The first SiN_(x) deposition is similar to previous versions with theexception that it is now included under the base contact pad (as well asthe collector pad) as shown in FIG. 6 b. This is a double safeguard forpad isolation. Now referring to FIG. 6 c, note that the metal depositionshown on the collector pad is altered. Ni and Pt are both high stressfilms, so Ti/Au was chosen as a replacement since Ti is low stress andAu prevents oxidation to underlying metals. In one particularembodiment, these are deposited at 500/1000 Å, respectively.

Collector fingers were also changed from Schottky to ohmic sincecollector and base metals were no longer to be deposited simultaneously.The new metal scheme is Ti/Ni (100/400 Å). Process tests support the useof a thicker Ni layer and removal of the Al layer and are the reason forthis increase in thickness. This thin metal is the maximum thicknessallowed with the thin (e.g., 1500 Å) e-beam resist needed for finefeatures (e.g., 0.15 μm). Following this metal liftoff, SiN_(x) isdeposited (as previously described with the two stage etch).

After the base metallization, the emitter is etched. This requires athick resist of, for instance, AZ4620 of about 4 μm. Dimensions of theemitter etch are given in FIG. 6 d, and the final device structure isshown in FIG. 6 e.

A fifth variation of the fabrication process includes a modification tothe silicon nitride pad deposited in steps 5, 5a, and 5b. In thisalternative embodiment, the SiN_(x) pad is square such that, the Heimplanted region will extend out to the collector fingers, and no SiNwill be under the fingers. This will reduce the difference in heightbetween the fingers in the collector pad region (e.g., view 3 of FIG. 2b) relative to the height of the fingers out of the collector pad region(e.g., view 4 of FIG. 2 b), which helps to prevent the metal fingersfrom disconnecting from the collector pad due to a significantdifference in height. One such alternative embodiment is shown in FIG.7, where there is only a layer of titanium under the fingers at thecollector pad region (and no SiN layer). Thus, the height difference ofthe collector fingers in the collector region and the collector fingersout of the collector region is about one layer of titanium.

FIG. 8 shows a top view SEM picture of a completed PBT device configuredin accordance with the present invention. As can be seen, high accuracyin the alignment of the different mask layers was achieved since thedevices were processed with an optical lithography alignment tolerancein the order of 1.5 μm. This tolerance is much smaller than the usuallimit for this technique.

FIG. 9 shows detailed SEM images of the collector finger of twodifferent devices, with device (a) having 1:1 finger pitch and device(b) having 1:3 finger pitch. One half the finger width (0.2 μm/2) is theeffective device channel and the base contact thickness (600 Å) is theequivalent gate length. Note that these values are very small whencompared to the conventional FET device features. Further note that aramp down from −400V bias to −200V bias during the etch step produced afairly smooth etched base surface. A finger sidewall angle ofapproximately 85° was achieved, which is highly anisotropic. A nickelmetal layer thickness of 400 Å acted as an excellent etch mask as can beappreciated by the uniform morphology of the finger structures.

Probing of the various CTLM test structures shows ohmic metal contactswhich have specific contact resistivity, ρ_(c), of about 3×10⁻⁶Ω·cm²,which is an indication of the excellent contact quality.

The DC characteristic curve of a device with 1:1 finger pitch is shownin FIG. 10. The output characteristics have been measured for an appliedbase-emitter bias V_(BE) ranging from +0.5 V to −1.0 V. Thecollector-emitter voltage V_(CE) is in the 0 V to 5.5 V range. From theplot, it is evident that the base voltage controls the output currentI_(C), showing transistor action. For V_(CE)=+5.0 V and V_(BE)=+0.5V, acurrent density J_(C) of up to 520 mA/mm² is achieved. DC testing of thedevices shows good base control (modulation Of I_(CE)), and currentdensities of up to 450 mA/mm² were achieved for a V_(CE) of 5.0V.

The foregoing description of the embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed. Many modifications and variations are possible in light ofthis disclosure. It is intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto.

1. A method for fabricating an etched grooved GaN-based permeable-basetransistor device, comprising: opening a window for helium implantationon a hydride vapor phase epitaxy (HVPE) grown n⁺ GaN quasi-substratelayer, using optical lithography; implanting helium on the n+ GaNquasi-substrate layer over the window for helium implantation, so as toprovide an insulating layer for contact pads of the device; opening awindow for collector fingers using E-beam lithography; depositing anohmic metallization layer over the window for the collector fingers;lifting-off ohmic metallization, thereby forming the collector fingers;opening a window for a self-aligned base recess using opticallithography; etching to recess a base layer to an n⁻ GaN quasi-substratelayer grown on the n⁺ GaN quasi-substrate layer, wherein the etching isperformed with a ramp down in chuck bias voltage wherein said ramp downis from a high chuck bias voltage to a low chuck bias voltage; opening awindow for a collector contact pad, using optical lithography;depositing a high quality silicon nitride layer over the window for acollector contact pad; and lifting-off or wet chemical etching the highquality silicon nitride layer, thereby forming a silicon nitridecollector contact pad.
 2. The method of claim 1 wherein the high qualitysilicon nitride layer is about approximately 1000-2000 Å thick, and isdeposited over the window for helium implantation via plasma enhancedchemical vapor deposition (PECVD).
 3. The method of claim 1 furthercomprising: opening a window for Ti metallization of the collectorcontact pad using optical lithography; depositing Ti over the window forTi metallization of the collector contact pad; and lifting-off Timetallization, thereby forming a Ti collector contact pad.
 4. The methodof claim 3 further comprising: opening a window for a second Timetallization of the collector contact pad using optical lithography;depositing Ti over the window for the second Ti metallization of thecollector contact pad; and lifting-off second Ti metallization, therebyforming a Ti cap over the collector contact pad.
 5. The method of claim1 wherein depositing Ti over the window for Ti metallization of thecollector contact pad includes depositing Ti/Au at thicknesses of aboutapproximately 500 Å/1000 Å, respectively, using e-beam evaporation. 6.The method of claim 1 further comprising: opening an emitteretch/contact window using optical lithography; etching an emitter recessto the n⁺ GaN quasi-substrate layer; depositing an emitter ohmicmetallization layer over the etched emitter recess; and lifting-offemitter ohmic metallization, thereby forming an emitter contact pad. 7.The method of claim 1 wherein the emitter ohmic metallization layerincludes at least one of titanium, aluminum, nickel, and gold.
 8. Themethod of claim 1 wherein the helium implantation is achieved with animplant depth of about approximately 2 μm.
 9. The method of claim 1wherein the ohmic metallization layer over the window for the collectorfingers is Ti/Ni with thicknesses of 100 Å and 400 Å, respectively. 10.The method of claim 1 wherein the device has a plurality of collectorfingers about approximately 0.2 Å wide and having a finger pitch between1:1 and 1:3.
 11. A method for fabricating an etched grooved GaN-basedpermeable-base transistor device, comprising: opening a window forhelium implantation on a hydride vapor phase epitaxy (HVPE) grown n⁺ GaNquasi-substrate layer, using optical lithography; implanting helium onthe n+ GaN quasi-substrate layer over the window for heliumimplantation, so as to provide an insulating layer for contact pads ofthe device; opening a window for collector fingers using E-beamlithography; depositing an ohmic metallization layer over the window forthe collector fingers; lifting-off ohmic metallization, thereby formingthe collector fingers; opening a window for a self-aligned base recessusing optical lithography; etching to recess a base layer to an n⁻ GaNquasi-substrate layer grown on the n⁺ GaN quasi-substrate layer, whereinthe etching is performed with a ramp down in chuck bias voltage;depositing conformal silicon nitride for passivation of the recessedbase layer; directionally etching to remove silicon nitride on planesparallel to the n⁺ GaN quasi-substrate layer; depositing a basemetallization layer; and lifting-off base metallization, thereby forminga base contact pad.
 12. The method of claim 11 further comprising basemetallization and wherein an anneal is performed after said basemetallization so as to provide the base contact pad with low reversecurrent leakage and low contact resistance.
 13. The method of claim 11wherein an emitter ohmic metallization layer includes at least one oftitanium, aluminum, nickel, and gold.
 14. The method of claim 11 whereinthe helium implantation is achieved with an implant depth of aboutapproximately 2 μm.
 15. The method of claim 11 wherein the ohmicmetallization layer over the window for the collector fingers is Ti/Niwith thicknesses of 100 Å and 400 Å, respectively.
 16. The method ofclaim 11 wherein the device has a plurality of collector fingers aboutapproximately 0.2 μm wide and having a finger pitch between 1:1 and 1:3.